One of the advantages of a time domain multiplexing scheme to transmit digital signals is that a plurality of digital signals or channel signals can be transmitted sharing a single transmission channel. For example, TDM is commonly applied in ASIC (application specific integrated circuit) and FPGA (field programmable gate array) designs to reduce pin counts used for communication to other chips. As chip densities have increased, pin counts have not kept pace making TDM based communication more attractive. In ASIC, prototypes may be built by mapping partitions of the ASIC design onto FPGAs. Because ASIC modules were designed to be connected on a single chip, they often have 5-10 times the connections between them as are available in IC packages. If a connection between chips is being shared many times per design clock cycle, then the performance of transmission will limit the speed of the system. Improvements in the TDM transmission rate are then highly valuable.
Typically, TDM is either synchronous or asynchronous Synchronous TDM can be high performance because signals to be transmitted can be assigned a single time slot per clock cycle, allowing efficient use of the available time. However, maintaining accurate clock synchronization between multiple ICs can be both expensive and difficult, requiring the creation and distribution of high frequency clocks associated with each clock involved in chip interconnection. Failure to maintain accurate synchronization between chips limits the rate of transmission. The use of source synchronous transmission and buffering in a FIFO (First In First Out) can be used to overcome the synchronization issue where latency is not important. However, in many uses such as ASIC prototyping, latency has tight constraints and a FIFO can't be used.
Asynchronous TDM uses a high frequency transmission clock that is not synchronized to the user clock. Instead, the data is sampled and transmitted multiple times per design clock cycle, such as describe in, for example, U.S. Pat. No. 7,007,254 entitled “Methods and Apparatus for the Design and Analysis of Digital Circuits with Time Division Multiplexing” to Drazen Borkovic and Kenneth S. McElvain. The virtues of the asynchronous scheme are that a single TDM clock can be distributed with loose synchronization constraints and there is no complex slot assignment to determine as the transmission slots are not synchronized to the design clocks anyway. In such a scheme the time between successive samples of a given design signal becomes part of the chip-to-chip delay. For high TDM ratios where many distinct signals are sharing the same channel, this oversampling delay can become quite large and is the major deficiency of the scheme.
Therefore, traditional TDM schemes fail to meet the performance and resource requirements in heavily interconnected multi-device systems such as ASIC prototypes and there is a need for improvement.